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CS3706GNF16 Folha de dados(PDF) 4 Page - ON Semiconductor |
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CS3706GNF16 Folha de dados(HTML) 4 Page - ON Semiconductor |
4 / 8 page 4 Outputs The totem-pole outputs have been designed to minimize cross-conduction current spikes while maximizing fast, high-current rise and fall times. Current limiting can be done externally either at the outputs or at the common VCC pin. The output diodes included have slow recovery and should be shunted with high-speed external diodes when driving high-frequency inductive loads. Flip/Flop Grounding F/F Enable activates the internal flip-flop to alternate the two outputs. With pin open, the two outputs operate simultaneously and can be paralleled for higher current operation. Since the flip-flop is triggered by the digital input, an off-time of at least 200nsec. must be pro- vided to allow the flip/flop to change states. Note that the circuit logic is configured such that the “OFF” state is defined as the outputs low. Digital Inputs With both an inverting and non-inverting input available, either active-high or active-low signals may be accepted. These are true TTL compatible inputs–the threshold is approximately 1.2V with no hysteresis; and external pull- up resistors are not required. Inhibit Circuit Although it may have other uses, this circuit is included to eliminate the need for deadband control when driving rel- atively slow bipolar power transistors. A diode from each inhibit input to the opposite power switch collector will keep one output from turning on until the other has turned-off. The threshold is determined by the voltage on INHIBIT REF which can be set from 0.5 to 3.5 V. When this circuit is not used, ground INHIBIT REF and leave INHIB- IT A&B open. Analog Shutdown This circuit is included to get a latched shutdown as close to the outputs as possible, from a time standpoint. With an internal 130mV threshold, this comparator has a common- mode range from ground to (VIN - 3V). When not used, both inputs should be grounded. The time required for this circuit to latch is inversely proportional to the amount of overdrive but reaches a minimum of 180nsec. As with the flip-flop, an input off-time of at least 200nsec is required to reset the latch between pulses. Supply Voltage With an internal 5V regulator, this circuit is optimized for use with a 7 to 40V supply, however, with some slight response time degradation, it can also be driven from 5V. When VIN is low, the entire circuit is disabled and no cur- rent is drawn from VCC. When combined with a CS384X PWM, the Driver Bias switch can be used to supply VIN to the CS3706. VIN switching should be fast as undefined operation of the outputs may occur with VIN less than 5V. Thermal Considerations Should the chip temperature reach approximately 155˚C, a parallel, non-inverting input is activated driving both out- puts to the low state. Circuit Description INV. N.I. OUT HH L LH H HL L LL L Truth Table OUT = INV and N.I. OUT = INV or N.I. |
Nº de peça semelhante - CS3706GNF16 |
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Descrição semelhante - CS3706GNF16 |
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