TMP105

SLLS648D

– FEBRUARY 2005 – REVISED SEPTEMBER 2011

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FAULT QUEUE (F1/F0)

programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of

environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert

function. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition in

Table 7. Fault Settings of the TMP105

F1

F0

CONSECUTIVE FAULTS

0

0

1

0

1

2

1

0

4

1

1

6

CONVERTER RESOLUTION (R1/R0)

The Converter Resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control

allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8

identifies the resolution bits and the relationship between resolution and conversion time.

Table 8. Resolution of the TMP105

CONVERSION TIME

R1

R0

RESOLUTION

(typical)

0

0

9 Bits (0.5

°C)

27.5ms

0

1

10 Bits (0.25

°C)

55ms

1

0

11 Bits (0.125

°C)

110ms

1

1

12 Bits (0.0625

°C)

220ms

ONE-SHOT (OS)

The TMP105 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,

writing a

‘1’ to the OS bit starts a single temperature conversion. The device will return to the shutdown state at

the completion of the single conversion. This option is useful to reduce power consumption in the TMP105 when

continuous temperature monitoring is not required. When the Configuration Register is read, the OS always

reads zero.

HIGH AND LOW LIMIT REGISTERS

In Comparator Mode (TM = 0), the ALERT pin of the TMP105 becomes active when the temperature equals or

faults.

consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register

occurs, or until the device successfully responds to the SMBus Alert Response address. The ALERT pin clears if

the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the

remains active until cleared by a read operation of any register or a successful response to the SMBus Alert

Response address. When the ALERT pin clears, the above cycle will repeat, with the ALERT pin becoming

device with the General Call Reset command. This reset also clears the state of the internal registers in the

device returning the device to Comparator Mode (TM = 0).

8

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