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MC10125L Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC10125L Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10125/D MC10125 Quad MECL to TTL Translator The MC10125 is a quad translator for interfacing data and control signals between the MECL section and saturated logic sections of digital systems. The MC10125 incorporates differential inputs and Schottky TTL “totem pole” outputs. Differential inputs allow for use as an inverting/ non–inverting translator or as a differential line receiver. The VBB reference voltage is available on pin 1 for use in single–ended input biasing. The outputs of the MC10125 go to a low logic level whenever the inputs are left floating. Power supply requirements are ground, +5.0 Volts and –5.2 Volts. Propagation delay of the MC10125 is typically 4.5 ns. The MC10125 has fanout of 10 TTL loads. The dc levels are MECL 10,000 in and Schottky TTL, or TTL out. This device has an input common mode noise rejection of ± 1.0 Volt. An advantage of this device is that MECL level information can be received, via balanced twisted pair lines, in the TTL equipment. This isolates the MECL logic from the noisy TTL environment. This device is useful in computers, instrumentation, peripheral controllers, test equipment and digital communications systems. • P D = 380 mW typ/pkg (No Load) • t pd = 4.5 ns typ (50% to + 1.5 Vdc out) • t r, tf = 2.5 ns typ (1.0 V to 2.0 V) LOGIC DIAGRAM 4 3 2 5 7 6 12 11 10 13 15 14 1 VBB* *VBB to be used to supply bias to the MC10125 only and bypassed (when used) with 0.01 µF to 0.1 µF capacitor to ground (0 V). VBB can source < 1.0 mA. When the input pin with the bubble goes positive, the output goes negative. Gnd = PIN 16 VCC (+5.0Vdc) = PIN 9 VEE (-5.2Vdc) = PIN 8 DIP PIN ASSIGNMENT VBB AIN AIN AOUT BOUT BIN BIN VEE GND DIN DIN DOUT COUT CIN CIN VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10125L CDIP–16 25 Units / Rail MC10125P PDIP–16 25 Units / Rail MC10125FN PLCC–20 46 Units / Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10125L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10125 AWLYYWW 1 1 16 MC10125P AWLYYWW |
Nº de peça semelhante - MC10125L |
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Descrição semelhante - MC10125L |
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