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SI5341 Folha de dados(PDF) 6 Page - Silicon Laboratories |
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SI5341 Folha de dados(HTML) 6 Page - Silicon Laboratories |
6 / 56 page Si5341/40 6 Rev. 1.0 Table 2. DC Characteristics (VDD =1.8 V ±5%, VDDA =3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units Core Supply Current IDD Si5341 Note 1 — 100 150 mA Si5340 Note 2 —85 130 mA IDDA Si5341 Note 1 —115 125 mA Si5340 Note 2 —115 125 mA Output Buffer Supply Current IDDOx LVPECL Output3 @ 156.25 MHz —21 25 mA LVDS Output3 @ 156.25 MHz —15 18 mA 3.3 V LVCMOS4 output @ 156.25 MHz —21 25 mA 2.5 V LVCMOS4 output @ 156.25 MHz —16 18 mA 1.8 V LVCMOS4 output @ 156.25 MHz —12 13 mA Total Power Dissipation Pd Si5341 Notes 1,5 — 830 980 mW Si5340 Notes 2,5 — 685 815 mW Notes: 1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an ac-coupled 100 load. 4. LVCMOS outputs measured into a 6-inch 50 PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on register settings. 5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. 50 50 100 OUT OUT IDDO Differential Output Test Configuration 0.1 uF 0.1 uF 50 OUTa IDDO 5 pF LVCMOS Output Test Configuration 6 inch OUTb |
Nº de peça semelhante - SI5341 |
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Descrição semelhante - SI5341 |
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