Os motores de busca de Datasheet de Componentes eletrônicos |
|
SI5380-EVB Folha de dados(PDF) 5 Page - Silicon Laboratories |
|
SI5380-EVB Folha de dados(HTML) 5 Page - Silicon Laboratories |
5 / 50 page Fin (MHz)1 LTE Device Clock Frequencies Fout (MHz)2 Note: 1. The Si5380 locks to any one of the frequencies listed in the Fin column and generates LTE device clock frequencies. 2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks. 3.1.2 Si5380 Configuration for JESD204B Clock Generation The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks (DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS- REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica- tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in- cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4), though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the 3.5.15 Output Skew Control (Δt0 - Δt4) section for details on skew control. The SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register writes. Si5380 IN_SEL[1:0] IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3b/FB_INb ÷P1 ÷P0 ÷P2 ÷P3 DSPLL LPF PD ÷M ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷N4 t4 OUT6b VDDO6 OUT6 VDDO7 VDDO0 OUT0Ab OUT0A OUT0b OUT0 ÷R6 ÷R0A OUT7b OUT7 ÷R7 OUT5b VDDO5 OUT5 ÷R5 OUT1b VDDO1 OUT1 VDDO2 ÷R1 OUT2b OUT2 ÷R2 OUT8b VDDO8 OUT8 ÷R8 OUT3b VDDO3 OUT3 VDDO4 ÷R3 OUT4b OUT4 ÷R4 VDDO9 OUT9b OUT9 OUT9Ab OUT9A ÷R9 ÷R0 ÷R9A Device Clocks SYSREF Clocks ÷N0 t0 ÷5 Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks Si5380 Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 0.96 | 4 |
Nº de peça semelhante - SI5380-EVB |
|
Descrição semelhante - SI5380-EVB |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |