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SI52112-B6 Folha de dados(PDF) 6 Page - Silicon Laboratories |
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SI52112-B6 Folha de dados(HTML) 6 Page - Silicon Laboratories |
6 / 20 page Si52112-B5/B6 6 Rev 1.2 Spread Range SRNG Down Spread, -B6 only — –0.5 — % Modulation Frequency FMOD -B6 only 30 31.5 33 kHz Enable/Disable and Set-up Clock Stabilization from Power- up TSTABLE —— 3 ms Stopclock Set-up Time TSS 10.0 — — ns Table 4. Thermal Conditions Parameter Symbol Test Condition Min Typ Max Unit Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case (TDFN) ØJC JEDEC (JESD 51) — — 38.3 °C/W Dissipation, Junction to Case (TSSOP) ØJC JEDEC (JESD 51) — — 37.0 °C/W Dissipation, Junction to Ambient (TDFN) ØJA JEDEC (JESD 51) — — 90.4 °C/W Dissipation, Junction to Ambient (TSSOP) ØJA JEDEC (JESD 51) — — 124.0 °C/W Table 5. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit Main Supply Voltage VDD_3.3V —— 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22 - A114) 2000 — — V Flammability Rating UL-94 UL (Class) V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup. Power supply sequencing is not required. Table 3. AC Electrical Specifications (Continued) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
Nº de peça semelhante - SI52112-B6 |
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Descrição semelhante - SI52112-B6 |
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