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SI53311 Folha de dados(PDF) 7 Page - Silicon Laboratories |
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SI53311 Folha de dados(HTML) 7 Page - Silicon Laboratories |
7 / 30 page Si53311 Preliminary Rev. 0.4 7 Table 9. AC Characteristics (VDD =1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Frequency F LVPECL, low power LVPECL, LVDS, CML, HCSL 1 — 1250 MHz LVCMOS 1 — 200 MHz Duty Cycle Note: 50% input duty cycle. DC 200 MHz, 50 toVDD/220/80% TR/TF<10% of period (LVCMOS) TBD TBD TBD % 20/80% TR/TF<10% of period (Differential) 48 50 52 % Minimum Input Clock Slew Rate1 SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF LVPECL, LVDS, CML, HCSL, 20/80% 350 ps 200 MHz, 50 20/80%, 2 pF load (LVCMOS) TBD TBD 750 ps Minimum Input Pulse Width TW 500 — — ps Additive Jitter (Differential Clock Input) JVDD = 2.5/3.3 V, LVPECL/LVDS, F = 725 MHz, 0.75 V/ns input slew rate —60 80 fs Propagation Delay TPLH, TPHL Low to high, high to low Single-ended TBD — TBD ns Low to high, high to low Differential TBD — TBD ns Output Enable Time2 TEN F=1MHz — 2 — s F = 100 MHz — 60 — ns F = 725 MHz — 50 — ns Output Disable Time2 TDIS F=1MHz — 2 — s F = 100 MHz — 25 — ns F = 725 MHz — 15 — ns Notes: 1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required. 2. See Figure 4. 3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (1.8V=50mVPP, 2.5/3.3V=100mVPP) and noise spur amplitude measured. See AN491 for further details. |
Nº de peça semelhante - SI53311 |
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Descrição semelhante - SI53311 |
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