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SI53312 Folha de dados(PDF) 11 Page - Silicon Laboratories |
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SI53312 Folha de dados(HTML) 11 Page - Silicon Laboratories |
11 / 33 page Si53312 Rev. 1.0 11 2. Functional Description The Si53312 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The selected clock input is routed to two independent banks of outputs. Each output bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength. 2.1. Universal, Any-Format Input The Si53312 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various input ac- and dc-coupling options supported by the device. Figures 3 and 4 show the recommended input clock termination options. Figure 2. Differential LVPECL, LVDS, CML AC-Coupled Input Termination Figure 3. LVCMOS DC-Coupled Input Termination Table 15. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 16. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes Yes (3.3 V) Yes No Si53312 0.1 µF 0.1 µF CLKx /CLKx 100 VDD Si53312 VDD 1 k CMOS Driver VTERM = VDD/2 CLKx = 3. 3 V or2. 5 V VDDO CLKx 50 Rs 1 k VREF |
Nº de peça semelhante - SI53312 |
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Descrição semelhante - SI53312 |
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