Os motores de busca de Datasheet de Componentes eletrônicos |
|
SI53315 Folha de dados(PDF) 1 Page - Silicon Laboratories |
|
SI53315 Folha de dados(HTML) 1 Page - Silicon Laboratories |
1 / 30 page Preliminary Rev. 0.4 10/12 Copyright © 2012 by Silicon Laboratories Si53315 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si53315 1:10 L OW J ITTER U NIVERSAL B UFFER/L EVEL TRANSLATOR WITH 2:1 I NPUT M UX AND I NDIVIDUAL OE (<1.25 GH Z) Features Applications Description The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable output clock signal format and individual OE. The Si53315 features a 2:1 mux, making it ideal for redundant clocking applications. The Si53315 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53315 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram 10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 MHz to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Asynchronous output enable Individual output enable Low output-output skew: <50 ps Low propagation delay variation: <400 ps Independent VDD and VDDO : 1.8/2.5/3.3 V Excellent power supply noise rejection (PSRR) Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 44-QFN (7 mm x 7 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution VREF Power Supply Filtering Vref Generator VDDOB OE[5:9] Q0, Q1, Q2, Q3, Q4 Q0, Q1, Q2, Q3, Q4 OE[0:4] VDDOA SFOUT[1:0] CLK0 CLK0 CLK1 CLK1 Q5, Q6, Q7, Q8, Q9 Q5, Q6, Q7, Q8, Q9 CLK_SEL Switching Logic Patents pending Ordering Information: See page 25. Pin Assignments Si53315 GND PAD 27 26 25 24 23 29 28 30 32 31 33 7 8 9 10 11 5 6 4 2 3 1 Q0 Q0 Q1 Q1 Q2 Q2 Q7 Q7 Q8 Q8 Q9 Q9 GND SFOUT[0] SFOUT[1] NC OE2 OE1 OE0 OE9 OE8 OE7 |
Nº de peça semelhante - SI53315 |
|
Descrição semelhante - SI53315 |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |