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CDCP1803RGERG4 Folha de dados(PDF) 10 Page - Texas Instruments

Nome de Peças CDCP1803RGERG4
Descrição Electrónicos  1:3 LVPECL CLOCK BUFFER
Download  25 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
Logo TI1 - Texas Instruments

CDCP1803RGERG4 Folha de dados(HTML) 10 Page - Texas Instruments

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I − Load − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
−5
0
5
10
15
20
25
30
35
VDD = 3.3 V
G004
CDCP1803
SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013
www.ti.com
CONTROL INPUT CHARACTERISTICS
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu
Setup time, S0, S1, S2, and EN terminals before clock IN
25
ns
th
Hold time, S0, S1, S2, and EN terminals after clock IN
0
ns
Time between latching the EN low transition and when all
t(disable)
outputs are disabled (how much time is required until the
10
ns
outputs turn off)
Time between latching the EN low-to-high transition and when
t(enable)
outputs are enabled based on control settings (how much time
1
μs
passes before the outputs carry valid signals)
Rpullup
Internal pullup resistor on S[2:0] and EN input
42
60
78
k
VIH(H)
Three-level input high, S0, S1, S2, and EN terminals(1)
0.9 VDD
V
VIL(L)
Three-level low, S0, S1, S2, and EN terminals
0.1 VDD
V
IIH
VI = VDD
–5
μA
Input current, S0, S1, S2, and EN terminals
IIL
VI = GND
38
85
μA
(1)
Leaving this terminal floating automatically pulls the logic level high to VDD through an internal pullup resistor of 60 kΩ.
BIAS VOLTAGE VBB
over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBB
Output reference voltage
VDD = 3 V–3.6 V, IBB = –0.2 mA
VDD – 1.4
VDD – 1.2
V
OUTPUT REFERENCE VOLTAGE (VBB)
vs
LOAD
Figure 5.
10
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Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links :CDCP1803


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