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CDCVF2310PW Folha de dados(PDF) 10 Page - Texas Instruments |
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CDCVF2310PW Folha de dados(HTML) 10 Page - Texas Instruments |
10 / 23 page CLK Gn Yn tsu(en) th(en) CLK Gn Yn tsu(dis) th(dis) a) Enable Mode b) Disable Mode CDCVF2310 SCAS666D – JUNE 2001 – REVISED OCTOBER 2015 www.ti.com 8.3 Feature Description 8.3.1 Output Enable Glitch Suppression Circuit The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the input clock) (see Figure 6). The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable operation. Figure 6. Enable and Disable Mode Relative to CLK ↓ 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: CDCVF2310 |
Nº de peça semelhante - CDCVF2310PW |
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Descrição semelhante - CDCVF2310PW |
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