Rev 2.1, May 2, 2008

Page 9 of 11

SL23EP04NZ

Output Duty Cycle

DC3

CL=15pF, Fout=80 MHz

Measured at VDD/2

45

50

55

%

Output Rise/Fall Time

tr/f-1

CL=15pF, measured at 0.6V to 1.7V

–

–

1.8

ns

Output Rise/Fall Time

tr/f-2

CL=30pF, measured at 0.6V to 1.7V

–

–

2.4

ns

Output to Output Skew

SKW1

Measured at VDD/2 and

Outputs are equally loaded

–

100

200

ps

Part to Part Skew

SKW2

Measured at VDD/2 and

Outputs are equally loaded

–

120

240

ps

Propagation Delay Time

PDT

Measured at VDD/2 from CLKIN to

Output Clock rising edge and Outputs

are equally loaded

–

4.2

6.8

ns

Cycle-to-Cycle Jitter

CCJ1

CLKIN=66MHz and CL=0 (No Load)

–

70

140

ps

Cycle-to-Cycle Jitter

CCJ2

CLKIN=133MHz and CL=0 (No Load)

–

60

120

ps

Power-up Time

tpu

Power-up time for VDD to reach

minimum specified time

0.05

–

100

ms

External Components & Design Considerations

Typical Application Schematic

SL23EP04NZ

0.1

μF

CLKIN

CLK2

CLK3

GND

VDD

1

6

4

8

5

3

CL

CLK1

CL

CL

CL

CLK4

7

OE

2

Comments and Recommendations

Decoupling Capacitor:

A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the

capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and

to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD

pin.

Package Outline and Package Dimensions