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SL23EP09ZI-1 Folha de dados(PDF) 4 Page - Silicon Laboratories |
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SL23EP09ZI-1 Folha de dados(HTML) 4 Page - Silicon Laboratories |
4 / 14 page Rev 2.0, May 12, 2008 Page 4 of 14 SL23EP09 S2 S1 Clock A1-A4 Clock B1-4 CLKOUT Output Source PLL Status 0 0 Tri-state Tri-state Driven PLL On 0 1 Driven Tri-state Driven PLL On 1 0 Driven Driven Driven Reference Off 1 1 Driven Driven Driven PLL On Table 2. Select Input Decoding 0 5 10 15 20 25 30 -30 -25 -20 -5 -10 -15 1500 1000 500 -500 -1500 -1000 0 Output Load Difference: FBK Load – CLKA or CLKB Load (pF) Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) |
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Descrição semelhante - SL23EP09ZI-1 |
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