Rev 2.1, May 6, 2008

Page 7 of 9

SL2304NZ

Switching Electrical Characteristics (I-Grade and VDD=3.3V)

Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C

Description

Symbol

Condition

Min

Typ

Max

Unit

Output Frequency Range

FOUT1

CL=15pF

DC

–

140

MHz

FOUT2

CL=30pF

DC

–

100

MHz

Output Rise/fall Time

tr/f-1

CL=15pF, measured at 0.8V to 2.0V

–

–

2.2

ns

Output Rise/Fall Time

tr/f-2

CL=30pF, measured at 0.8V to 2.0V

–

–

2.6

ns

Input Duty Cycle

DC1

Measured at VDD/2

20

–

80

%

Output Duty Cycle

DC2

CL=15pF, Fout=140MHz

Measured at VDD/2

45

–

55

%

Output Duty Cycle

DC3

CL=30pF, Fout=100MHz

Measured at VDD/2

40

–

60

%

Output to Output Skew

SKW1

Measured at VDD/2 and

Outputs are equally loaded

–

60

120

ps

Part to Part Skew

SKW2

Measured at VDD/2 and

Outputs are equally loaded

–

120

240

ps

Propagation Delay Time

PDT

Measured at VDD/2 from CLKIN to

Output Clock rising edge and Outputs

are equally loaded

1.2

2.5

3.8

ns

Cycle-to-Cycle Jitter

CCJ1

CLKIN=66MHz and CL=15

–

80

160

ps

Cycle-to-Cycle Jitter

CCJ2

CLKIN=133MHz and CL=15

–

60

120

ps

External Components & Design Considerations

Typical Application Schematic

SL2304NZ

0.1

μF

CLKIN

CLK2

CLK3

GND

VDD

1

6

4

8

5

3

CL

CLK1

CL

CL

CL

CLK4

7

OE

2

Recommendations

Decoupling Capacitor:

A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the

capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and

to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD

pin.