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SI4737 Folha de dados(PDF) 5 Page - Silicon Laboratories |
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SI4737 Folha de dados(HTML) 5 Page - Silicon Laboratories |
5 / 69 page AN383 Rev. 0.8 5 2. Si47xx 3x3 mm QFN Schematic and Layout This section shows the minimal schematic and layout options required for optimal Si47xx performance. Population options are provided to support a single layout for all 3 x 3 mm QFN devices, mitigate system noise, operate the internal oscillator with an external crystal, and filter VCO energy. 2.1. Si47xx 3x3 mm Design C1 (22 nF) is a required bypass capacitor for VD/VDD supply pin 11. Place C1 as close as possible to the VD/VDD pin 11 and GND pin 12. Place a via connecting C1 VD/VDD supply to the power rail such that the cap is closer to the Si47xx than the via. Route C1 GND directly and only to GND pin 12 with a wide, low inductance trace. C1 GND should not be routed to GND via. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the GND pad. Note: For Si47xx rev D parts, C1 is required on pin 11 (VA ). The C1 design guidelines described above should be followed. For an illustration of these guidelines, refer to Figure 3. C2 (22 nF) is an optional bypass capacitor for VA/LIN/DFS supply pin 16 (Si4702/03 only) and may be placed to mitigate supply noise. Place C2 as close as possible to the VA/LIN/DFS pin 16 and GND pin 15. Place a via connecting C2 VA supply to the power rail such that the cap is closer to the Si47xx than the via. Route C2 GND directly and only to GND pin 15 with a wide, low inductance trace. Route GND/RIN/DOUT pin 15 to the GND pad if designing only for the Si4702/03. If designing for all Si47xx devices, do not route GND/RIN/DOUT pin 15 to the GND pad. In this case the on-chip connection between pin 15 and the GND pad will provide a ground connection. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the GND pad. C3 (100 nF) is an optional bypass capacitor for the VIO supply pin 10 and may be placed to mitigate supply noise. Place C3 as close as possible to the VIO pin 10 and the GND pin 12. Place a via connecting C3 VIO supply to the power rail such that the cap is closer to the Si47xx than the via. Route C3 GND directly and only to GND pin 12 with a wide, low inductance trace. C3 GND should not be routed to GND via. These recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize bypass cap impedance and return all currents to the GND pad. Note: For Si47xx rev D parts, C3 is required on pin 10 (VD) . The C3 design guidelines described above should be followed. C6 and C7 (0.39µF) are ac coupling caps for transmitter audio input to VA/LIN/DFS pin 16 and GND/RIN/DOUT pin 15 (Si471x/2x analog audio input mode only). The input resistance of the transmitter audio input and the cap will set the high pass pole given by Equation 1. The input resistance of the audio input is programmatically selectable as 396 k , 100 k, 74 k, or 60 k (default). Placement location is not critical. Equation 1. High-Pass Pole Calculation C8 and C9 (0.39 µF.) are ac coupling caps for receiver analog audio output from ROUT/DIN pin 13 and LOUT/DFS pin 14 (Si470x/2x/3x/8x audio output mode only). The input resistance of the amplifier, such as a headphone amplifier, and the capacitor will determine the high pass pole given by Equation 1. Placement location is not critical. C10 and C11 (7–22 pF) are optional crystal loading caps required only when using the internal oscillator feature. Refer to the crystal data sheet for the proper load capacitance and be certain to account for parasitic capacitance. Place caps C10 and C11 such that they share a common GND connection and the current loop area of the crystal and loading caps is minimized. C12 and C13 (2.2 pF) are noise mitigation caps if digital audio option is in use. The caps need to be placed close to the Si47xx chip. X1 (32.768 kHz) is an optional crystal required only when using the internal oscillator feature. Place the crystal X1 as close to GPO3/DCLK pin 17 and RCLK pin 9 as possible to minimize current loops. Route the RCLK trace as far from SDIO pin 8 and SDIO trace as possible to minimize capacitive coupling. R1 (0 ) is an optional jumper used to route the digital audio clock to GPO3/DCLK pin 17. R1 is only required for a universal design which accommodates BOM population options selecting between crystal and digital audio (Si4705/06/1x/2x/31/35/37/39/8x only). fc 1 2 RC ---------------- = |
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