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TS7001 Folha de dados(PDF) 5 Page - Silicon Laboratories |
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TS7001 Folha de dados(HTML) 5 Page - Silicon Laboratories |
5 / 21 page TS7001 TS7001 Rev. 1.0 Page 5 TIMING SPECIFICATIONS1 VDD = +2.7V to +3.6V; TA = TMIN to TMAX, unless otherwise noted. Parameter Limit Unit Description fSCLK 2 3 MHz (max) External serial clock tCONVERT 14.5 × tSCLK Conversion Time tACQ 1.5 × tSCLK Throughput Time = tCONVERT + tACQ = 16 tSCLK t1 10 ns (min) CS to SCLK Setup Time t2 3 60 ns (max) Delay from CS until DOUT three-state disabled t3 3 100 ns (max) Data Access Time after SCLK High-to-Low Edge t4 20 ns (min) Data Setup Time prior to SCLK Low-to-High Edge t5 20 ns (min) Data Valid to SCLK Hold Time t6 0.4 × tSCLK ns (min) SCLK high Pulse Width t7 0.4 × tSCLK ns (min) SCLK low Pulse Width t8 4 80 ns (max) CS rising edge to DOUT High-Z t9 5 μs (typ) Power-up Time from Shutdown Note 1: Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed relative to a voltage level of 1.6V. Note 2: The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details. Note 3: Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V. Note 4: Timing specification t8 is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the TS7001 and is independent of bus loading. Load Circuit Used for TS7001’s Digital Output Timing Specifications. |
Nº de peça semelhante - TS7001 |
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Descrição semelhante - TS7001 |
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