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DAC5681ZIRGCR Folha de dados(PDF) 3 Page - Texas Instruments |
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DAC5681ZIRGCR Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 61 page 45 42 DAC5681Z GND CLKINC D4P D4N D3P D3N D2P D2N DVDD D1P D1N D0P D0N VFUSE SDO SDIO SCLK SDENB D12N D12P D13N D13P D14N D14P DVDD D15N D15P IOVDD SYNCN SYNCP CLKIN CLKVDD 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 47 46 44 43 41 40 39 38 37 36 35 34 33 48 1 DAC5681Z www.ti.com SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015 5 Pin Configuration and Functions RGC Package 64-Pin VQFN Top View Pin Functions PIN I/O DESCRIPTION NAME NO. 51, 54, 55, AVDD I Analog supply voltage. (3.3 V) 59–62 BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960- Ω resistor to GND. Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL CLKIN 2 I enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides clock for DAC up to 1 GHz. CLKINC 3 I Complementary external clock input. (See the CLKIN description) CLKVDD 1 I Internal clock buffer supply voltage. (1.8 V) LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100- Ω 7, 11, 13, termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format 15, 17, 19, relative to DCLKP/N clock is double data rate (DDR) with two data samples input per DCLKP/N clock. In 21, 23, 27, D[15..0]P I dual-channel mode, data for the A-channel is input while DCLKP is high. 29, 31, 33, 35, 37, 40, D15P is most significant data bit (MSB) – pin 7 42 D0P is least significant data bit (LSB) – pin 42 Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC5681Z |
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