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DAC5681ZIRGCT Folha de dados(PDF) 11 Page - Texas Instruments |
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DAC5681ZIRGCT Folha de dados(HTML) 11 Page - Texas Instruments |
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11 / 61 page  DAC5681Z www.ti.com SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015 Electrical Characteristics – Digital Specifications (continued) over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8-V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB VIH High-level input voltage 2 3 V VIL Low-level input voltage 0 0 0.8 V IIH High-level input current ±20 μA IIL Low-level input current ±20 μA CMOS Input CI 5 pF capacitance IOVDD Iload = –100 μA V –0.2 VOH SDO, SDIO 0.8 x Iload = –2mA V IOVDD Iload = 100 μA 0.2 V VOL SDO, SDIO Iload = 2 mA 0.5 V Set-up time, SDENB to ts(SDENB) 20 ns rising edge of SCLK Set-up time, SDIO valid ts(SDIO) 10 ns to rising edge of SCLK Hold time, SDIO valid th(SDIO) 5 ns to rising edge of SCLK t(SCLK) Period of SCLK 100 ns t(SCLKH) High time of SCLK 40 ns t(SCLKL) Low time of SCLK 40 ns Data output delay after td(Data) 10 ns falling edge of SCLK Minimum RESETB tRESET 25 ns pulse width CLOCK INPUT (CLKIN/CLKINC) Duty cycle 50% Differential voltage(3) 0.4 1 V CLKIN/CLKINC input CLKVDD V common mode ÷2 (3) Driving the clock input with a differential voltage lower than 1 V will result in degraded performance. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC5681Z |
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