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DAC34SH84IZAY Folha de dados(PDF) 9 Page - Texas Instruments |
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DAC34SH84IZAY Folha de dados(HTML) 9 Page - Texas Instruments |
9 / 93 page DAC34SH84 www.ti.com SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015 Electrical Characteristics – DC Specifications (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(AVDD) Analog supply current(4) 115 mA Mode 7 I(DIGVDD) Digital supply current 335 mA fDAC = 1 GSPS, 2x interpolation, I(DACVDD) DAC supply current 23 mA mixer off,QMC off, invsinc off, I(CLKVDD) Clock supply current 70 mA PLL disabled, 20-mA FS output, IF = 7.3 MHz P Power dissipation 940 mW I(AVDD) Analog supply current(4) 45 mA Mode 8 I(DIGVDD) Digital supply current 655 mA fDAC = 1.47456 GSPS, 2× interpolation, I(DACVDD) DAC supply current mixer on, QMC on, invsinc on, 30 mA PLL disabled, IF = 7.3 MHz, channels A/B/C/D I(CLKVDD) Clock supply current 95 mA output sleep P Power dissipation 1169 mW 6.6 Electrical Characteristics – Digital Specifications over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1) Logic-high differential VA,B+ input voltage 200 mV threshold Logic-low differential VA,B– input voltage –200 mV threshold VCOM Input common mode 1 1.2 1.6 V ZT Internal termination 85 110 135 Ω LVDS input CL 2 pF capacitance Interleaved LVDS fINTERL 1500 MSPS data transfer rate fDATA Input data rate 750 MSPS CLOCK INPUT (DACCLKP/N) Differential voltage(2) |DACCLKP - DACCLKN| 0.4 1 V Internally biased common-mode 0.2 V voltage Single-ended swing –0.4 V level OUTPUT STROBE (OSTRP/N) Differential voltage |OSTRP-OSTRN| 0.4 1.0 V Internally biased common-mode 0.2 V voltage Single-ended swing –0.4 V level CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA High-level input 0.7 × VIH V voltage IOVDD2 Low-level input 0.3 × VIL V voltage IOVDD2 High-level input IIH –40 40 µA current (1) See LVDS Inputs section for terminology. (2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC34SH84 |
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