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DAC121S101QCMK Folha de dados(PDF) 7 Page - Texas Instruments |
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DAC121S101QCMK Folha de dados(HTML) 7 Page - Texas Instruments |
7 / 37 page DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J – JUNE 2005 – REVISED SEPTEMBER 2015 Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) TYP (1) MAX (1) UNIT TA = 25°C 1.43 VA = 5.5 V mW TMIN ≤ TA ≤ TMAX 1.72 Normal Mode fSCLK = 30 MHz TA = 25°C 0.64 VA = 3.6 V mW TMIN ≤ TA ≤ TMAX 0.78 TA = 25°C 1.23 VA = 5.5 V mW TMIN ≤ TA ≤ TMAX 1.53 Normal Mode fSCLK = 20 MHz TA = 25°C 0.57 VA = 3.6 V mW TMIN ≤ TA ≤ TMAX 0.71 VA = 5.5 V 0.84 µW Power Consumption (output Normal Mode PC unloaded) fSCLK = 0 VA = 3.6 V 0.42 µW VA = 5 V 0.42 µW All PD Modes, fSCLK = 30 MHz VA = 3 V 0.13 µW VA = 5 V 0.28 µW All PD Modes, fSCLK = 20 MHz VA = 3 V 0.08 µW TA = 25°C 0.39 VA = 5.5 V µW TMIN ≤ TA ≤ TMAX 5.5 All PD Modes, fSCLK = 0 (2) TA = 25°C 0.14 VA = 3.6 V µW TMIN ≤ TA ≤ TMAX 3.6 VA = 5 V 91% IOUT / IA Power Efficiency ILOAD = 2 mA VA = 3 V 94% 7.6 AC and Timing Characteristics The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCLK SCLK Frequency TMIN ≤ TA ≤ TMAX 30 MHz TA = 25°C 8 CL ≤ 400h to C00h µs TMIN ≤ TA ≤ 200 pF code change, 10 TMAX RL = 2 kΩ Output Voltage Settling ts CL = 500 pF 12 µs Time (1) 00Fh to FF0h CL ≤ 200 pF 8 µs code change, CL = 500 pF 12 µs RL = 2 kΩ SR Output Slew Rate 1 V/µs Glitch Impulse Code change from 800h to 7FFh 12 nV-s Digital Feedthrough 0.5 nV-s VA = 5 V 6 µs tWU Wake-Up Time VA = 3 V 39 µs 1/fSC SCLK Cycle Time TMIN ≤ TA ≤ TMAX 33 ns LK TA = 25°C 5 tH SCLK High time ns TMIN ≤ TA ≤ TMAX 13 TA = 25°C 5 tL SCLK Low Time ns TMIN ≤ TA ≤ TMAX 13 TA = 25°C −15 Set-up Time SYNC to tSUCL ns SCLK Rising Edge TMIN ≤ TA ≤ TMAX 0 TA = 25°C 2.5 tSUD Data Set-up Time ns TMIN ≤ TA ≤ TMAX 5 (1) This parameter is specified by design and/or characterization and is not tested in production. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DAC121S101 DAC121S101-Q1 |
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