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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ACE25Q800G Folha de dados(PDF) 9 Page - ACE Technology Co., LTD. |
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ACE25Q800G Folha de dados(HTML) 9 Page - ACE Technology Co., LTD. |
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9 / 47 page  ACE25Q800G 8M BIT SPI NOR FLASH Memory Series VER 1.1 9 SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground). LB3/LB2/LB1 bit The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS bit The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle. Status Register Protect Table (Table5) SRP1 SRP0 /WP Status Register Description 0 0 X Software Protected The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) 0 1 0 Hardware Protected /WP=0, the Status Register locked and cannot be written. 0 1 1 Hardware Unprotected /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down (1) Status Register is protected and cannot be written To again until the next Power-Down, Power-Up cycle. 1 1 X One Time Program (2) Status Register is permanently protected and cannot be written to. Notes: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. The One time Program feature is available upon special order. Please contact ACE for details. |
Nº de peça semelhante - ACE25Q800G |
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Descrição semelhante - ACE25Q800G |
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