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74F823SC Folha de dados(PDF) 3 Page - National Semiconductor (TI) |
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74F823SC Folha de dados(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Functional Description The ’F823 device consists of nine D-type edge-triggered flip-flops It has TRI-STATE true outputs and is organized in broadside pinning The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops The flip- flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition With the OE LOW the contents of the flip- flops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect the state of the flip-flops In addi- tion to the Clock and Output Enable pins the ’F823 has Clear (CLR) and Clock Enable (EN) pins When the CLR is LOW and the OE is LOW the outputs are LOW When CLR is HIGH data can be entered into the flip- flops When EN is LOW data on the inputs is transferred to the outputs on the LOW to HIGH clock transition When the EN is HIGH the outputs do not change state regardless of the data or clock inputs transitions This device is ideal for parity bus interfacing in high performance systems Function Table Inputs Internal Output Function OE CLR EN CP D Q O H H L H X NC Z Hold H H L L X NC Z Hold H H H X X NC Z Hold L H H X X NC NC Hold H L X X X H Z Clear L L X X X H L Clear HH L L H H Z Load HH L L H L Z Load LH L L L H L Data Available LH L L H L H Data Available L H L H X NC NC No Change in Data L H L L X NC NC No Change in Data L e LOW Voltage Level H e HIGH Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TLF9596 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3 |
Nº de peça semelhante - 74F823SC |
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Descrição semelhante - 74F823SC |
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