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FM1608-120-S Folha de dados(PDF) 3 Page - Ramtron International Corporation |
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FM1608-120-S Folha de dados(HTML) 3 Page - Ramtron International Corporation |
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3 / 12 page  Ramtron FM1608 28 July 2000 3/12 Overview The FM1608 is a bytewide FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard parallel interface. The FM1608 is inherently nonvolatile via its unique ferroelectric process. All data written to the part is immediately nonvolatile with no delay. Functional operation of the FRAM memory is similar to SRAM type devices. The major operating difference between the FM1608 and an SRAM (beside nonvolatile storage) is that the FM1608 latches the address on the falling edge of /CE. Memory Architecture Users access 8,192 memory locations each with 8 data bits through a parallel interface. The complete address of 13-bits specifies each of the 8,192 bytes uniquely. Internally, the memory array is organized into 8 blocks of 1Kb each. The 3 most-significant address lines decode one of 8 blocks. This block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance requirements as explained in a later section. The access and cycle time are the same for read and write memory operations. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. A pre-charge operation, where /CE goes inactive, is a part of every memory cycle. Thus unlike SRAM, the FM1608 access and cycle times are not equal. Note that the FM1608 has no special power-down demands. It will not block user access and it contains no power-management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. Memory Operation The FM1608 is designed to operate in a manner very similar to other bytewide memory products. For users familiar with BBSRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the obvious differences result from the higher write performance of FRAM technology including NoDelay writes and much higher write endurance. Read Operation A read operation begins on the falling edge of /CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a complete memory cycle must be completed internally regardless of the state of /CE. Data becomes available on the bus after the access time has been satisfied. After the address has been latched, the address value may change upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. The FM1608 will drive the data bus when /OE is asserted to a low state. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients due to invalid data. When /OE is inactive the data bus will remain tri-stated. Write Operation Writes occur in the FM1608 in the same time interval as reads. The FM1608 supports both /CE and /WE controlled write cycles. In all cases, the address is latched on the falling edge of /CE. In a /CE controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the part begins the memory cycle as a write. The FM1608 will not drive the data bus regardless of the state of /OE. In a /WE controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls after the falling edge of /CE. Therefore the memory cycle begins as a read. The data bus will be driven according to the state of /OE until /WE falls. The timing of both /CE and /WE controlled write cycles is shown in the electrical specifications. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever is first. Data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus |
Nº de peça semelhante - FM1608-120-S |
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Descrição semelhante - FM1608-120-S |
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