AD6643BCPZRL7-250 datasheet(11/40 Pages) AD

Nome de Peças	AD6643BCPZRL7-250

Descrição Electrónicos	Dual IF Receiver

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Fabricante Electrônico	AD [Analog Devices]

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Data Sheet

AD6643

Rev. C | Page 11 of 40

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CLK+

CLK–

SYNC

DNC

DRVDD

DNC

D0– (LSB)

D0+ (LSB)

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

PDWN

OEB

CSB

SCLK

SDIO

OR+

OR–

D10+ (MSB)

D10– (MSB)

D9+

D9–

DRVDD

D8+

D8–

D7+

D7–

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AD6643

INTERLEAVED

PARALLEL

LVDS

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 4. Pin Configuration (Top View), LFCSP Interleaved Parallel LVDS

Table 8. Pin Function Descriptions for the Interleaved Parallel LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54, 59, 60, 63, 64

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

4 to 9, 11 to 14, 55, 56, 58

DNC

Do Not Connect. Do not connect to these pins.

0

AGND,

Exposed

Paddle

Ground

Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the device. This exposed paddle

must be connected to ground for proper operation.

ADC Analog

51

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

52

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

62

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

61

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

57

VCM

Output

Common-Mode Level Bias Output for Analog Inputs. This pin should be

decoupled to ground using a 0.1 μF capacitor.

1

CLK+

Input

ADC Clock Input—True.

2

CLK−

Input

ADC Clock Input—Complement.

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

15

D0− (LSB)

Output

Channel A/Channel B LVDS Output Data 0—True.

16

D0+ (LSB)

Output

Channel A/Channel B LVDS Output Data 0—Complement.

18

D1+

Output

Channel A/Channel B LVDS Output Data 1—True.

17

D1−

Output

Channel A/Channel B LVDS Output Data 1—Complement.

21

D2+

Output

Channel A/Channel B LVDS Output Data 2—True.

20

D2−

Output

Channel A/Channel B LVDS Output Data 2—Complement.

23

D3+

Output

Channel A/Channel B LVDS Output Data 3—True.

22

D3−

Output

Channel A/Channel B LVDS Output Data 3—Complement.

27

D4+

Output

Channel A/Channel B LVDS Output Data 4—True.

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