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ADC1005 Folha de dados(PDF) 7 Page - National Semiconductor (TI) |
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ADC1005 Folha de dados(HTML) 7 Page - National Semiconductor (TI) |
7 / 12 page Block Diagram Functional Description 1.0 GENERAL OPERATION A block diagram of the A/D converter is shown in Figure 1. All of the inputs and outputs are shown and the major logic con- trol paths are drawn in heavier weight lines. 1.1 Converter Operation The ADC1005 uses an advanced potentiometric resistive ladder network. The analog inputs, as well as the taps of this ladder network are switched into a weighted capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows the successive ap- proximation logic to match the analog input voltage [V IN(+) – V IN(−)] to taps on the R network. The most significant bit is tested first and after 10 comparisons (80 clock cycles) a digi- tal 10-bit binary code (all “1”s = full-scale) is transferred to an output latch. 1.2 Starting a Conversion The conversion is initialized by taking CS and WR simulta- neously low. This sets the start flip-flop (F/F) and the result- ing “1” level resets the 10-bit shift register, resets the inter- rupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 10-bit shift register. Internal clock sig- nals then transfer this “1” to the Q ouput of F/F1. The AND gate, G1, combines this “1” output with a clock signal to pro- vide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 10-bit shift register then can have the “1” clocked in, allowing the conversion process to continue. If the set signal were still present, this reset pulse would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR sig- nals. The converter will start after at least one of these sig- nals returns high and the internal clocks again provide a re- set signal for the start F/F. To summarize, on the high-to-low transition of the WR input the internal SAR latches and the shift register stages are re- set. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start after at least one of these inputs makes a low-to-high transition. 1.3 Output Control After the “1” is clocked through the 10-bit shift register (which completes the SAR search) it causes the new digital word to transfer to the TRI-STATE output latches. When the XFER DS005261-11 Note 9: CS shown twice for clarity. Note 10: SAR=Successive Approximation Register. FIGURE 1. www.national.com 7 |
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