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ADC1005BCJ-1 Folha de dados(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças ADC1005BCJ-1
Descrição Electrónicos  10-Bit P Compatible A/D Converter
Download  12 Pages
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC1005BCJ-1 Folha de dados(HTML) 9 Page - National Semiconductor (TI)

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Functional Description (Continued)
change in the common-mode voltage during this short time
interval can cause conversion errors. For a sinusoidal
common-mode signal, this error is:
where f
CM is the frequency of the common-mode signal,
V
PEAK is its peak voltage value and fCLK is the clock fre-
quency at the CLK IN pin.
For a 60 Hz common-mode signal to generate a 14 LSB error
(1.2 mV) with the converter running at 1.8 MHz, its peak
value would have to be 1.46V. A common-mode signal this
large is much greater than that generally found in data aqui-
sition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short dura-
tion spikes of current enter the “+” input and exit the “−” input
at the clock rising edges during the conversion. These cur-
rents decay rapidly and do not cause errors as the internal
comparator is strobed at the end of a clock period.
3.3 Input Bypass Capacitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the V
IN(+) input voltage at full scale. For continuous
conversions with a 1.8 MHz clock frequency with the V
IN(+)
input at 5V, this DC current is at a maximum of approxi-
mately 5 µA. Therefore,
bypass capacitors should not be
used at the analog inputs or the VREF pin for high resistance
sources (>1k
Ω). If input bypass capacitors are necessary
for noise filtering and high source resistance is desirable to
minimize capacitor size, the detrimental effects of the volt-
age drop across this input resistance, which is due to the av-
erage value of the input current, can be eliminated with a
full-scale adjustment while the given source resistor and in-
put bypass capacitor are both in place. This is possible be-
cause the average value of the input current is a linear func-
tion of the differential input voltage.
3.4 Input Source Resistance
Large values of source resistance where an input bypass ca-
pacitor is not used,
will not cause errors if the input currents
settle out prior to the comparison time. If a low pass filter is
required in the system, use a low valued series resistor (
≤1
k
Ω) for a passive RC section or add an op amp RC active
low pass filter. For low source resistance applications (
≤0.1
k
Ω) a 4700 pF bypass capacitor at the inputs will prevent
pickup due to series lead induction of a long wire. A 100
Ω se-
ries resistor can be used to isolate this capacitor – both the
R and the C are placed outside the feedback loop – from the
output of an op amp, if used.
3.5 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these in-
puts should, in general, be kept below 1 k
Ω. Larger values of
source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog in-
puts to ground, can reduce system noise pickup but can cre-
ate analog scale errors. See section 3.2, 3.3, and 3.4 if input
filtering is to be used.
4.0 OFFSET AND REFERENCE ADJUSTMENT
4.1 Zero Offset
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V(−) input and applying a small magnitude
positive voltage to the V(+) input. Zero error is the difference
between the actual DC input voltage that is necessary to just
cause an output digital code transition from 00 0000 0000 to
00 0000 0001 and the ideal 12 LSB value (12 LSB = 2.45 mV
for V
REF = 5.0 VDC).
The zero of the A/D normally does not require adjustment.
However, for cases where V
IN(MIN) is not ground and in re-
duced span applications (V
REF < 5V), an offset adjustment
may be desired. The converter can be made to output an all
zero digital code for an arbitrary input by biasing the A/D’s
V
IN(−) input at that voltage. This utilizes the differential input
operation of the A/D.
4.2 Full Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage that is 112 LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
nitude of the V
REF input for a digital output code that is just
changing from 11 1111 1110 to 11 1111 1111.
4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
that does not go to ground), this new zero reference should
be properly adjusted first. A V
IN(+) voltage that equals this
desired zero reference plus 12 LSB (where the LSB is calcu-
lated for the desired analog span, 1 LSB = analog span/
1024) is applied to selected “+” input and the zero reference
voltage at the corresponding “−” input should then be ad-
justed to just obtain the 000
HEX 001HEX code transition.
The full-scale adjustment should be made [with the proper
V
IN(−) voltage applied] by forcing a voltage to the VIN(+) in-
put given by:
where V
MAX = the high end of the analog input range and
V
MIN = the low end (the offset zero) of the analog range.
(Both are ground referenced).
The V
REF (or VCC) voltage is then adjusted to provide a code
change from 3FF
HEX to 3FEHEX. This completes the adjust-
ment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.
5.0 POWER SUPPLIES
Noise spikes on the V
CC supply line can cause conversion
errors as the comparator will respond to this noise. A low in-
ductance tantalum filter capacitor should be used close to
the converter V
CC pin and values of 1 µF or greater are rec-
ommended. If an unregulated voltage is available in the sys-
www.national.com
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