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AM3894CCYG135 Folha de dados(PDF) 1 Page - Texas Instruments |
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AM3894CCYG135 Folha de dados(HTML) 1 Page - Texas Instruments |
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1 / 313 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM3894 AM3892 SPRS681G – OCTOBER 2010 – REVISED MARCH 2015 AM389x Sitara™ ARM® Microprocessors (MPUs) 1 Device Overview 1.1 Features 1 – Dynamic Memory Manager (DMM) • High-Performance Sitara ARM® Microprocessors (MPUs) • Programmable Multi-Zone Memory Mapping and Interleaving – ARM Cortex™-A8 RISC Processor • Enables Efficient 2D Block Accesses • Up to 1.20 GHz • Supports Tiled Objects in 0°, 90°, 180°, or • ARM Cortex-A8 Core 270° Orientation and Mirroring – ARMv7 Architecture • Optimizes Interlaced Accesses • In-Order, Dual-Issue, Superscalar Processor • One PCI Express® (PCIe) 2.0 Port with Integrated Core PHY • NEON™ Multimedia Architecture – Single Port with 1 or 2 Lanes at 5.0 GT per – Supports Integer and Floating Point (VFPv3- Second IEEE754 Compliant) – Configurable as Root Complex or Endpoint • Jazelle® RCT Execution Environment • Serial ATA (SATA) 3.0 Gbps Controller with • ARM Cortex-A8 Memory Architecture Integrated PHYs – 32-KB Instruction and Data Caches – Direct Interface for Two Hard Disk Drives – 256-KB L2 Cache – Hardware-Assisted Native Command Queuing – 64-KB RAM, 48-KB of Boot ROM (NCQ) from up to 32 Entries • 512KB of On-Chip Memory Controller (OCMC) – Supports Port Multiplier and Command-Based RAM Switching • SGX530 3D Graphics Engine (Available Only on • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet the AM3894 Device) MACs (EMAC) – Delivers up to 30 MTriangles per Second – IEEE 802.3 Compliant (3.3-V I/O Only) – Universal Scalable Shader Engine – MII and GMII Media Independent Interfaces – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, – Management Data I/O (MDIO) Module OpenVG™ 1.1, OpenMax™ API Support • Dual USB 2.0 Ports with Integrated PHYs – Advanced Geometry DMA Driven Operation – USB 2.0 High-Speed and Full-Speed Client – Programmable HQ Image Anti-Aliasing – USB 2.0 High-Speed, Full-Speed, and Low- • Endianness Speed Host – ARM Instructions and Data – Little Endian – Supports Endpoints 0-15 • HD Video Processing Subsystem (HDVPSS) • General-Purpose Memory Controller (GPMC) – Two 165-MHz HD Video Capture Channels – 8-Bit and 16-Bit Multiplexed Address and Data • One 16-Bit or 24-Bit and One 16-Bit Channel Bus • Each Channel Splittable Into Dual 8-Bit – Up to 6 Chip Selects with up to 256-MB Address Capture Channels Space per Chip Select Pin – Two 165-MHz HD Video Display Channels – Glueless Interface to NOR Flash, NAND Flash • One 16-Bit, 24-Bit, 30-Bit Channel and One (with BCH and Hamming Error Code Detection), 16-Bit Channel SRAM and Pseudo-SRAM – Simultaneous SD and HD Analog Output – Error Locator Module (ELM) Outside of GPMC – Digital HDMI 1.3 Transmitter with PHY with to Provide up to 16-Bit and 512-Byte Hardware HDCP up to 165-MHz Pixel Clock ECC for NAND – Three Graphics Layers – Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces • Enhanced Direct-Memory-Access (EDMA) – Supports up to DDR2-800 and DDR3-1600 Controller – Up to Eight x8 Devices Total – Four Transfer Controllers – 2GB of Total Address Space 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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