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ADC10158CIWM Folha de dados(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças ADC10158CIWM
Descrição Electrónicos  10-Bit Plus Sign 4 關s ADCs with 4- or 8-Channel MUX, Track/Hold and Reference
Download  23 Pages
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC10158CIWM Folha de dados(HTML) 6 Page - National Semiconductor (TI)

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Electrical Characteristics
The following specifications apply for V
+ = AV+ = DV+ = + 5.0 V
DC,VREF
+ = 5.000 V
DC,VREF
= GND, V= GND for unipolar
operation or V
= −5.0 V
DC for bipolar operation, and fCLK = 5.0 MHz unless otherwise specified. Boldface limits apply for TA
= T
J = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 16)
Symbol
Parameter
Conditions
Typical
Limits
(Note 11)
Units
(Limit)
(Note 10)
AC CHARACTERISTICS
f
CLK
Clock Frequency
8
5.0
MHz (Max)
10
kHz (Min)
Clock Duty Cycle
20
% (Min)
80
% (Max)
t
C
Conversion
8-Bit Unipolar Mode
16
1/f
CLK
Time
f
CLK = 5.0 MHz
3.2
µs (Max)
8-Bit Bipolar Mode
18
1/f
CLK
f
CLK = 5.0 MHz
3.6
µs (Max)
10-Bit Unipolar Mode
20
1/f
CLK
f
CLK = 5.0 MHz
4.0
µs (Max)
10-Bit Bipolar Mode
22
1/f
CLK
f
CLK = 5.0 MHz
4.4
µs (Max)
t
A
Acquisition Time
6
1/f
CLK
f
CLK = 5.0 MHz
1.2
µs
t
CR
Delay between Falling Edge of
0
5
ns (Min)
CS and Falling Edge of RD
t
RC
Delay betwee Rising Edge
0
5
ns (Min)
RD and Rising Edge of CS
t
CW
Delay between Falling Edge
0
5
ns (Min)
of CS and Falling Edge of WR
t
WC
Delay between Rising Edge
0
5
ns (Min)
of WR and Rising Edge of CS
t
RW
Delay between Falling Edge
0
5
ns (Min)
of RD and Falling Edge of WR
t
W(WR)
WR Pulse Width
25
50
ns (Min)
t
WS
WR High to CLK÷2 Low Set-Up Time
5
ns (Max)
t
DS
Data Set-Up Time
6
15
ns (Max)
t
DH
Data Hold Time
0
5
ns (Max)
t
WR
Delay from Rising Edge
0
5
ns (Min)
of WR to Rising Edge RD
t
ACC
Access Time (Delay from Falling
C
L = 100 pF
25
45
ns (Max)
Edge of RD to Output Data Valid)
t
WI,tRI
Delay from Falling Edge
C
L = 100 pF
25
40
ns (Max)
of WR or RD to Reset of INT
t
INTL
Delay from Falling Edge of CLK÷2to
Falling Edge of INT
40
ns
t
1H,t0H
TRI-STATE Control (Delay from
C
L = 10 pF, RL = 1kΩ
20
35
ns (Max)
Rising Edge of RD to Hi-Z State)
t
RR
Delay between Successive
25
50
ns (Min)
RD Pulses
t
P
Delay between Last Rising Edge
of RD and the Next Falling
20
50
ns (Min)
Edge of WR
C
IN
Capacitance of Logic Inputs
5
pF
C
OUT
Capacitance of Logic Outputs
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
www.national.com
6


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