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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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FM24V01A-GTR Folha de dados(PDF) 9 Page - Cypress Semiconductor |
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FM24V01A-GTR Folha de dados(HTML) 9 Page - Cypress Semiconductor |
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9 / 19 page  FM24V01A Document Number: 001-90869 Rev. *H Page 9 of 19 Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB (R/W) set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24V01A acknowledges the address, the bus master issues a START condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a '1'. The operation is now a current address read. Sleep Mode A low-power mode called Sleep Mode is implemented on the FM24V01A device. The device will enter this low power state when the Sleep command 86h is clocked-in. Sleep Mode entry can be entered as follows: 1. The master sends a START command. 2. The master sends Reserved Slave ID 0xF8. 3. The FM24V01A sends an ACK. 4. The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a 'Don't care' value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 5. The FM24V01A sends an ACK. 6. The master sends a Re-START command. 7. The master sends Reserved Slave ID 0x86. 8. The FM24V01A sends an ACK. 9. The master sends STOP to ensure the device enters sleep mode. Once in sleep mode, the device draws IZZ current, but the device continues to monitor the I2C pins. Once the master sends a Slave Address that the FM24V01A identifies, it will "wakeup" and be ready for normal operation within tREC (400 s max.). As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. While the device is waking up, it will NACK the master until it is ready. Figure 14. Selective (Random) Read S A Slave Address 1 Data Byte 1 P By Master By F-RAM Start Address Stop No Acknowledge Data S A Slave Address 0 Address MSB A Start Address Acknowledge Address LSB A Figure 15. Sleep Mode Entry S A P By Master By F-RAM Start Address Stop S A Rsvd Slave ID (F8) Slave Address A Start Address Acknowledge Rsvd Slave ID (86) X |
Nº de peça semelhante - FM24V01A-GTR |
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Descrição semelhante - FM24V01A-GTR |
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