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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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FM25V40-GCTR Folha de dados(PDF) 5 Page - Cypress Semiconductor |
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FM25V40-GCTR Folha de dados(HTML) 5 Page - Cypress Semiconductor |
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5 / 23 page  PRELIMINARY FM25V40 Document Number: 001-87288 Rev. *A Page 5 of 23 For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins. Figure 4 shows such a configuration, which uses only three pins. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit (MSB). This is valid for both address and data transmission. The 4-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only 19 bits, the first five bits, which are fed in are ignored by the device. Although these five bits are ‘don’t care’, Cypress recommends that these bits be set to 0s to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. FM25V40 uses the standard opcodes for memory accesses. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin until the next falling edge of CS, and the SO pin remains tristated. Status Register FM25V40 has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These bits are described in Table 3 on page 7. SPI Modes FM25V40 may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ SPI Mode 0 (CPOL = 0, CPHA = 0) ■ SPI Mode 3 (CPOL = 1, CPHA = 1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 5 on page 6 and Figure 6 on page 6. The status of the clock when the bus master is not transferring data is: ■ SCK remains at 0 for Mode 0 ■ SCK remains at 1 for Mode 3 Figure 3. System Configuration with SPI Port Figure 4. System Configuration without SPI Port CS 1 CS 2 HO L D 1 HO L D 2 FM25V40 FM25V40 WP1 WP2 SCK SI SO SCK SI SO CS HOLD WP CS HOLD WP SCK MOSI MISO SPI Microcontroller FM25V40 Microcontroller SCK SI SO CS HOLD WP P1.2 P1.1 P1.0 |
Nº de peça semelhante - FM25V40-GCTR |
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Descrição semelhante - FM25V40-GCTR |
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