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AD9229BCP-65 Folha de dados(PDF) 5 Page - Analog Devices |
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AD9229BCP-65 Folha de dados(HTML) 5 Page - Analog Devices |
5 / 15 page Preliminary Technical Data AD9229 Rev. PrF | Page 5 of 15 Oct. 6, 2003 Parameter Temp Test Level AD9229BCP-50 Min Typ Max AD9229BCP-65 Min Typ Max Unit CROSSTALK Full V -80 -80 dB Table 3: AC Specifications SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT Parameter Temp Test Level AD9229BCP-50 Min Typ Max AD9229BCP-65 Min Typ Max Unit Clock Rate Full VI 10 50 10 65 MSPS Clock Pulse Width High (tEH) Full IV ns CLOCK Clock Pulse Width Low (tEL) Full IV ns Valid Time (tV)1 Full VI ns Propagation Delay (tPD)1 Full VI 5 5 ns MSB Propagation Delay (tMSB)1 Full VI 5 5 ns Rise Time (tR) (20% to 80%) Full V ns Fall Time (tF) (20% to 80%) Full V ns DCO Propagation Delay (tCPD) Full VI 5 5 ns Data to DCO Skew (tPD – tCPD) Full IV ns OUTPUT PARAMETERS IN LVDS MODE Pipeline Latency Full VI 9 9 cycles Aperture Delay (tA) 25 °C V ps APERTURE Aperture Uncertainty (Jitter) 25 °C V <1 <1 ps rms Out of Range Recovery Time Full IV 2 2 cycles Table 4: Switching Specifications EXPLANATION OF TEST LEVELS TEST LEVEL I 100% production tested. II 100% production tested at +25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range. 1 tV and tPD are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 20% to 80%. |
Nº de peça semelhante - AD9229BCP-65 |
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Descrição semelhante - AD9229BCP-65 |
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