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DM54LS299W Folha de dados(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças DM54LS299W
Descrição Electrónicos  8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM54LS299W Folha de dados(HTML) 4 Page - National Semiconductor (TI)

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Functional Description
The ’LS299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left shift right parallel load and hold operations The
type of operation is determined by the S0 and S1 as shown
in the Mode Select Table All flip-flop outputs are brought
out through TRI-STATE buffers to separate IO pins that
also serve as data inputs in the parallel load mode Q0 and
Q7 are also brought out on other pins for expansion in serial
shifting of longer words
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops All other state changes are initiated
by the rising edge of the clock Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times relative to the rising edge of CP are
observed
A HIGH signal on either OE1orOE2 disables the TRI-
STATE buffers and puts the IO pins in the high impedance
state In this condition the shift hold load and reset opera-
tions can still occur The TRI-STATE buffers are also dis-
abled by HIGH signals on both S0 and S1 in preparation for
a parallel load operation
Mode Select Table
Inputs
Response
MR S1 S0 CP
L
X
X
X
Asynchronous Reset Q0 – Q7 e LOW
HH
H
L Parallel Load IOnxQn
HL
H
L Shift Right DS0xQ0 Q0xQ1 etc
HH
L
L Shift Left DS7xQ7 Q7xQ6 etc
H
L
L
X
Hold
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
4


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