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ADC08L060 Folha de dados(PDF) 3 Page - Texas Instruments |
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ADC08L060 Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 28 page GND VA ADC08L060 www.ti.com SNAS167G – MAY 2002 – REVISED MARCH 2013 Table 1. Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description 6 VIN Analog signal input. Conversion range is VRB to VRT. Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs 3 VRT define the VIN conversion range. Bypass well. See Section 2.0 for more information. Mid-point of the reference ladder. This pin should be bypassed to a 9 VRM quiet point in the analog ground plane with a 0.1 µF capacitor. Analog Input that is the low side (bottom) of the reference ladder of the ADC. Nominal range is 0.0V to (VRT – 0.5V). Voltage on VRT 10 VRB and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. Power Down input. When this pin is high, the converter is in the 23 PD Power Down mode and the data output pins hold the last conversion result. CMOS/TTL compatible digital clock Input. VIN is sampled on the 24 CLK rising edge of CLK input. 13 thru 16 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. and D0–D7 Valid data is output after the rising edge of the CLK input. 19 thru 22 7 VIN GND Reference ground for the single-ended analog input, VIN. Positive analog supply pin. Connect to a quiet voltage source of +3V. VA should be bypassed with a 0.1 µF ceramic chip capacitor 1, 4, 12 VA for each pin, plus one 10 µF capacitor. See Section 3.0 for more information. Power supply for the output drivers. If connected to VA, decouple 18 VDR well from VA. 17 DR GND The ground return for the output driver supply. 2, 5, 8, 11 AGND The ground return for the analog supply. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC08L060 |
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Descrição semelhante - ADC08L060_15 |
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