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AM5728BABCX Folha de dados(PDF) 5 Page - Texas Instruments

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Nome de Peças AM5728BABCX
Descrição Electrónicos  AM572x Sitara??Processors
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
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AM5728BABCX Folha de dados(HTML) 5 Page - Texas Instruments

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AM5728, AM5726
www.ti.com
SPRS953A – DECEMBER 2015 – REVISED JUNE 2016
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Product Folder Links: AM5728 AM5726
Revision History
Copyright © 2015–2016, Texas Instruments Incorporated
2
Revision History
Changes from December 18, 2015 to June 3, 2016 (from * Revision (December 2015) to A Revision)
Page
PCIe Specification Revision is updated to version 3.0
........................................................................... 1
Ecc support is removed from Figure 1-1
........................................................................................... 3
Ecc support is removed from Table 3-1
........................................................................................... 6
Added ”Related Products” section
.................................................................................................. 8
Clarification notes are added on rtc_porz and rtc_iso connections
........................................................... 10
Added footnotes to the vout3_* signals which are muxed on vddshv6 power balls in Table 4-2 Ball Characteristics
. 12
Added footnotes to the vout3_* signals which are muxed on vddshv6 power balls in Table 4-5 DSS Signal
Descriptions
........................................................................................................................ 115
Signal Descriptions updated to remove redundancy
.......................................................................... 118
Text in ESD Ratings table clarified
.............................................................................................. 159
Table 5-3 is updated to show 100k(POH) at 105°C for OPP_NOM.
........................................................ 160
Note (5) in Table 5-7 is updated
................................................................................................. 165
“Added “Power Consumption Summary” section
.............................................................................. 182
PCIe Specification Revision is updated to version 3.0
........................................................................ 190
Notes 9, 12 and 13 in Figure 5-1 are updated
................................................................................. 194
Fixed some of the descriptions on GPMC and QSPI Manual Modes names in Table 7-2 “Modes Summary”
....... 213
Added new Manual Modes for: VOUT1, VOUT2 IOSET1, VOUT2 IOSET2 and VOUT3. Removed
DSS_VIRTUAL1
................................................................................................................... 213
Removed PRU-ICSS Virtual I/O Modes
........................................................................................ 213
New Timing information available for: Video Input Ports (VIP), Display Subsystem – Video Output Ports,
Multichannel Serial Peripheral Interface (MCSPI), Quad Serial Peripheral Interface (QSPI) and eMMC/SD/SDIO.
213
Corrected references for McASP Virtual modes in Table 7-2 “Modes Summary”
........................................ 213
Removed all vin4b_* signals from Table 7-9 Manual Functions Mapping for VIP2
....................................... 224
A caution and two notes are added in “Display Subsystem – Video Output Ports“ section stating that VOUT
signals are recommended to not use the default SLEWCONTROL settings. Slow SLEWCONTROL should be
used instead.
....................................................................................................................... 234
Flipped the "Parameter" entries for D5 and D6 in Table 7-16
............................................................... 234
Added footnotes to the vout3_* signals which muxed on vddshv6 power balls in Table 7-18 VOUT3 IOSETs.
..... 237
A new caution is added in “Quad Serial Peripheral Interface” subsection
................................................. 280
QSPI time value Q7 direction on Figure 7-37 through Figure 7-40 is updated to start prior CS
....................... 282
Added Table 7-53 through Table 7-60 to clarify the MCASP Virtual Timing Mode usage
............................... 292
An update is performed in the “Peripheral Component Interconnect Express (PCIe)” section.
......................... 307
Updated/Changed MIN and MAX values for tw(DATAIN) in Table 7-136 and tw(CLOCKOUT) in Table 7-137................. 348
A clarification note is added in the “PRU-ICSS MII_RT Electrical Data and Timing” section
............................ 351
Removed section PRU-ICSS Virtual Function Mapping
..................................................................... 361
In Table 8-1 some of the pins connected to LDO3 and LDO4 are updated
............................................... 377
Aligning "Device and Documentation Support" section with new flow
...................................................... 406
Аdded SR 2.0 in Table 9-1
....................................................................................................... 407
Updated Yy parameter in Table Nomenclature Description
.................................................................. 407


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