CDC319

1-LINE TO 10-LINE CLOCK DRIVER

SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001

4

POST OFFICE BOX 655303

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 6.5 V

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–0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . .

48 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

120

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

_C

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† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,

which use a trace length of zero.

recommended operating conditions (see Note 3)

MIN

TYP

MAX

UNIT

VCC

3.3-V core supply voltage

3.135

3.465

V

A, OE

2

VCC+0.3

V

VIH

High-level input voltage

SDATA, SCLOCK

(see Note 3)

2.2

5.5

V

A, OE

–0.3

0.8

V

VIL

Low-level input voltage

SDATA, SCLOCK

(see Note 3)

0

1.04

V

IOH

High-level output current

Y outputs

– 24

mA

IOL

Low-level output current

Y outputs

24

mA

RI

Input resistance to VCC

SDATA, SCLOCK

(see Note 3)

140

k

Ω

f(SCL)

SCLOCK frequency

100

kHz

t(BUS)

Bus free time

4.7

µs

tsu(START)

START setup time

4.7

µs

th(START)

START hold time

4

µs

tw(SCLL)

SCLOCK low pulse duration

4.7

µs

tw(SCLH)

SCLOCK high pulse duration

4

µs

tr(SDATA)

SDATA input rise time

1000

ns

tf(SDATA)

SDATA input fall time

300

ns

tsu(SDATA)

SDATA setup time

250

ns

th(SDATA)

SDATA hold time

0

ns

tsu(STOP)

STOP setup time

4

µs

TA

Operating free-air temperature

0

70

°C

NOTE 3: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC.