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ABSOLUTE MAXIMUM RATINGS

CDC2536

SCAS377E – APRIL 1994 – REVISED JULY 2004

FUNCTIONAL BLOCK DIAGRAM (continued)

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Clock input. CLKIN provides the clock signal to be distributed by the CDC2536 clock-driver circuit. CLKIN

provides the reference signal to the integrated PLL that generates the clock output signals. CLKIN must

CLKIN

3

I

have a fixed frequency and fixed phase for the phase-lock loop to obtain phase lock. Once the circuit is

powered up and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lock

the feedback signal to its reference signal.

CLR

24

I

CLR is used for testing purposes only. Connect CLR to GND for normal operation.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of

FBIN

26

I

the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to

obtain zero phase delay between the FBIN and differential CLKIN inputs.

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE

is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly

OE

5

I

from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,

when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required

before the PLL obtains phase lock.

Output configuration select. SEL selects the output configuration for each output bank (e.g. 1

×, 1/2×, or

SEL

4

I

2

×).(see Tables 1 and 2).

TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs

TEST

25

I

operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses

the PLL circuitry. TEST should be grounded for normal operation.

These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The

relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle

1Y1-1Y3

7, 10, 13

O

of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Each output

has an internal series resistor to dampen transmission-line effects and improve the signal integrity at the

load.

These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency

and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty

2Y1-2Y3

22, 19, 16

O

cycle of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. Each

output has an internal series resistor to dampen transmission-line effects and improve the signal integrity at

the load.

UNIT

-0.5 V to 4.6 V

-0.5 V to 7 V

-0.5 V to 5.5 V

24 mA

-20 mA

-50 mA

0.68 W

-65

°C to 150°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

The maximum package power dissipation is calculated using a junction temperature of 150

°C and a board trace length of 75 mils. For

more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002B.

4