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CDCF5801 Folha de dados(PDF) 10 Page - Texas Instruments |
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CDCF5801 Folha de dados(HTML) 10 Page - Texas Instruments |
10 / 22 page www.ti.com PARAMETER MEASUREMENT INFORMATION TESTING CONDITIONS CLKOUT 10 pF 50 Ω 50 Ω CLKOUTB VCM CLKOUT CLKOUTB tCYCLE(i) Cycle-to-Cycle Jitter (t(jitter)) = | tCYCLE(i) - tCYCLE(i+1) | over 1000 consecutive cycles tCYCLE(i+1) Not Recommended for New Designs CDCF5801 SCAS698F – SEPTEMBER 2003 – REVISED APRIL 2006 STATE TRANSITION LATENCY SPECIFICATIONS (continued) TEST PARAMETER FROM TO MIN TYP MAX UNIT CONDITION Delay time, power up to CLKOUT 3 output settled t(VDDpowerup) VDD Normal See Figure 6 ms Delay time, power up to internal PLL 3 and clock are on and settled MULT0 and MULT1 change to t(MULT) Normal Normal See Figure 7 1 ms CLKOUT output resettled STOPB ↑ to CLKOUT glitch-free clock t(CLKON) CLK stop Normal See Figure 8 10 ns edges STOPB ↑ to CLKOUT output settled to t(CLKSETL) within 50 ps of the phase before CLK stop Normal See Figure 8 20 cycles STOPB was disabled t(CLKOFF) STOPB ↓ to CLKOUT output disabled Normal CLK stop See Figure 8 5 ns Delay time, PWRDNB ↓ to the device t(powerdown) Normal Power down See Figure 6 1 ms in the power-down mode Maximum time in CLKSTOP (STOPB t(STOP) = 0) before reentering normal mode STOPB Normal See Figure 8 100 µs (STOPB = 1) Minimum time in normal mode t(ON) (STOPB = 1) before reentering Normal CLK stop See Figure 8 100 ms CLKSTOP (STOPB = 0) Figure 1. Test Load and Voltage Definitions VOH, VOL, VO(STOP) Figure 2. Cycle-to-Cycle Jitter 10 Submit Documentation Feedback |
Nº de peça semelhante - CDCF5801 |
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Descrição semelhante - CDCF5801 |
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