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CDCR61APWRG4 Folha de dados(PDF) 5 Page - Texas Instruments |
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CDCR61APWRG4 Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 15 page CDCR61A DIRECT RAMBUS ™ CLOCK GENERATOR – LITE SCAS626 – FEBRUARY 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT IDD Static supply current Outputs high or low (VDDP = 0 V) 6.5 mA IDDL Static supply current (LVCMOS) Outputs high or low (VDDP = 0 V) 50 µA IDD(NORMAL) Supply current in normal state 300 MHz 39 mA IDD(NORMAL) Supply current in normal state 400 MHz 50 mA IDDL(NORMAL) Supply current in normal state (LVCMOS) 400 MHz 8 mA † VDD refers to any of the following; VDD, VDDL, and VDDP ‡ All typical values are at VDD = 3.3 V, VDDL = 1.8 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT t(cycle) Clock cycle time (CLK, CLKB) 2.5 3.7 ns t j Total jitter over 1, 2, 3, 4, 5, or 6 300 MHz See Figure 3 140 ps tcj j ,,,,, clock cycles‡ 400 MHz See Figure 3 100 ps tjL Long term jitter 300 MHz See Figure 4 400 ps tjL Long-term jitter 400 MHz See Figure 4 300 ps tDC Output duty cycle over 10,000 cycles See Figure 5 45% 55% tDC ERR Output cycle to cycle duty cycle error 300 MHz See Figure 6 70 ps tDC,ERR Output cycle-to-cycle duty cycle error 400 MHz See Figure 6 55 ps tr, tf Output rise and fall times (measured at 20%-80% of output voltage)# CLK, CLKB See Figure 9, 160 400 ps ∆t Difference between rise and fall times on a single device (20%–80%) |tf – tr|# See Figure 9, 100 ps tc(LCLK) Clock cycle time (LCLK) 106.6 142.2 ns t(cj) LCLK cycle jitter§ See Figure 11 –0.2 0.2 ns t(cj10) LCLK 10-cycle jitter§¶ See Figure 11 –1.3 t(cj) 1.3 t(cj) ns tDC Output duty cycle LCLK 40% 60% tr, tf Output rise and fall times (measured at 20%-80% of output voltage) LCLK See Figure 9 1 ns PLL loop bandwidth fmod = 50 kHz –3 dB PLL loop bandwidth fmod = 8 MHz –20 dB † All typical values are at VDD = 3.3 V, TA = 25°C. ‡ Output short-term jitter specification is peak-to-peak (see Figure 9). § LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period. ¶ LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter. # VDD= 3.3 V |
Nº de peça semelhante - CDCR61APWRG4 |
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Descrição semelhante - CDCR61APWRG4 |
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