Os motores de busca de Datasheet de Componentes eletrônicos |
|
AD9238 Folha de dados(PDF) 3 Page - Analog Devices |
|
AD9238 Folha de dados(HTML) 3 Page - Analog Devices |
3 / 24 page AD9238 –3– DC SPECIFICATIONS Test AD9238BST-20 AD9238BST-40 AD9238BST-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Low Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA Input Capacitance Full V 2 2 2 pF LOGIC OUTPUTS* DRVDD = 3.3 V High Level Output Voltage Full IV 3.29 3.29 3.29 V (IOH = 50 mA) High Level Output Voltage Full IV 3.25 3.25 3.25 V (IOH = 0.5 mA) Low Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 mA) Low Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) DRVDD = 2.5 V High Level Output Voltage Full IV 2.49 2.49 2.49 V (IOH = 50 mA) High Level Output Voltage Full IV 2.45 2.45 2.45 V (IOH = 0.5 mA) Low Level Output Voltage Full IV 0.05 0.05 0.05 V (IOL = 50 mA) Low Level Output Voltage Full IV 0.2 0.2 0.2 V (IOL = 1.6 mA) *Output Voltage Levels measured with 5 pF load on each output. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Test AD9238BST-20 AD9238BST-40 AD9238BST-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Max Conversion Rate Full VI 20 40 65 MSPS Min Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulsewidth High1 Full V 15.0 8.8 6.2 ns CLK Pulsewidth Low1 Full V 15.0 8.8 6.2 ns DATA OUTPUT PARAMETERS Output Delay2 (tPD) Full IV 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms OUT-OF-RANGE RECOVERYTIME Full V 1 1 2 Cycles NOTES 1The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20). 2Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output. 3Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Specifications subject to change without notice. (continued) REV. A |
Nº de peça semelhante - AD9238 |
|
Descrição semelhante - AD9238 |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |