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SM28VLT32-HT Folha de dados(PDF) 4 Page - Texas Instruments |
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SM28VLT32-HT Folha de dados(HTML) 4 Page - Texas Instruments |
4 / 16 page SM28VLT32-HT SLVSAO2C – NOVEMBER 2012 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS: MEMORY VIO = 3.1 V to 3.6 V, VCore = 1.8 V to 1.98 V, TJ = –55°C to 210°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tLife Continuous operating life 1000 hrs IDDVCORE 127 160 mA IDDVIO 14 22 mA Erase current -55°C to 125°C 76 mA Program current 85 mA Sector erase time -55°C to 125°C 2 3 s Program time 1 16-bit word 30 300 µs Nf Flash endurance for the array TJ = 30°C 1000 cycles (write/erase cycles) ELECTRICAL CHARACTERISTICS: SPI (1) (2) VIO = 3.1 V to 3.6 V, VCore = 1.8 V to 1.98 V, TJ = –55°C to 210°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCK SPI input clock frequency(3) 10 MHz fCLK Flash clock(3) 12 MHz tWH Clock high time 25 ns tWL Clock low time 25 ns tSU1 CS# setup time before SCK 15 ns tSU2 SI setup time before SCK 10 ns tOEN CS# to SO enabled CL = 16 pF 5 16.5 ns tDIS CS# to SO disabled(4) CL = 16 pF 5 16.5 ns tHD Data hold time after SCK 5 ns tr/tf 10% to 90% on all input pins 20 ns tV Clock low to data valid CL = 50 pF 15 30 ns (1) See Figure 3. (2) AC parameters apply to tr/tf of 5 ns. (3) The ratio of fCLK/fSCK must be 6/5 or higher to insure proper asynchronous operation. Operation below 12 MHz is acceptable, however, some configuration changes are required to set proper internal timing. See Provisions for Operating With fCLK Frequencies Less than 12 MHz for details if planned fCLK usage is below 12 MHz. (4) Disable parameters are specified when the outputs are no longer driven. 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: SM28VLT32-HT |
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