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LM34925 Folha de dados(PDF) 3 Page - Texas Instruments

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Nome de Peças LM34925
Descrição Electrónicos  Integrated Secondary-Side Bias Regulator for Isolated DC-DC Converters
Download  27 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
Logo TI1 - Texas Instruments

LM34925 Folha de dados(HTML) 3 Page - Texas Instruments

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SW
BST
VCC
FB
8
7
6
5
1
2
3
4
UVLO
RON
RTN
VIN
WSON-8
Exp Pad
UVLO
3
RON
4
RTN
1
VIN
2
8
SW
7
BST
6
VCC
5
FB
SO
PowePAD-8
Exp Pad
LM34925
www.ti.com
SNVS846F – JUNE 2012 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
NGU Package
8-Pin WSON With Exposed Thermal Pad
Top View
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NO.
NAME
1
RTN
Ground
Ground connection of the integrated circuit.
2
VIN
I
Input Voltage
Operating input range is 7.5 V to 100 V.
Resistor divider from VIN to UVLO to GND programs the undervoltage
Input Pin of Undervoltage
detection threshold. An internal current source is enabled when UVLO is
3
UVLO
I
Comparator
above 1.225 V to provide hysteresis. When UVLO pin is pulled below
0.66 V externally, the parts goes in shutdown mode.
A resistor between this pin and VIN sets the switch on-time as a function
4
RON
I
On-Time Control
of VIN. Minimum recommended on-time is 100ns at max input voltage.
This pin is connected to the inverting input of the internal regulation
5
FB
I
Feedback
comparator. The regulation level is 1.225 V.
Output from the Internal
High Voltage Series Pass
The internal VCC regulator provides bias supply for the gate drivers and
6
VCC
O
Regulator. Regulated at
other internal circuitry. A 1.0-
μF decoupling capacitor is recommended.
7.6 V.
An external capacitor is required between the BST and SW pins (0.01-
μF
7
BST
I
Bootstrap Capacitor
ceramic). The BST pin capacitor is charged by the VCC regulator through
an internal diode when the SW pin is low.
Power switching node. Connect to the output inductor and bootstrap
8
SW
O
Switching Node
capacitor.
Exposed pad must be connected to RTN pin. Connect to system ground
EP
Exposed Pad
plane on application board for reduced thermal resistance.
Copyright © 2012–2014, Texas Instruments Incorporated
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