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SN74ALVC3651-15PQ Folha de dados(PDF) 9 Page - Texas Instruments |
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SN74ALVC3651-15PQ Folha de dados(HTML) 9 Page - Texas Instruments |
9 / 29 page SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 output-ready flag The OR flag of a FIFO is synchronized to CLKB. When OR is high, new data is present in the FIFO output register. When OR is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. When a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition of CLKB occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register. A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 6). input-ready flag The IR flag of a FIFO is synchronized to the CLKA. When the IR flag is high, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. When a word is read from a FIFO, its previous memory location can be written in a minimum of three cycles of CLKA; therefore, an IR flag is low if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second low-to-high transition on CLKA after the read sets the IR flag high, and data can be written in the following cycle. A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 7). almost-empty flag The AE flag of a FIFO is synchronized to CLKB. The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The AE flag is low when the FIFO contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk(2), or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 8). |
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