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Detailed Description

Autoflow Control (see Figure 1)

RCV

FIFO

Serial to

Parallel

Flow

Control

XMT

FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT

FIFO

RCV

FIFO

ACE1

ACE2

D7 −D0

RX

TX

RTS

CTS

TX

RX

CTS

RTS

D7 −D0

Auto-RTS (See Figure 2 and Figure 3)

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

FN NO.

RHB NO.

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock

input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator

XTAL1

11

4

I

circuit (see Figure 5). Alternatively, an external clock can be connected to XTAL1 to provide

custom data rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal

XTAL2

13

5

O

oscillator output or buffered a clock output.

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before

the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data

and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless

the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a

TLC16C2552 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds

the receiver FIFO read latency.

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and

is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of

1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an

additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because

it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is

automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 5), RTS is deasserted after the first data bit of the 16th character is

present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.

5

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