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CAP1203-2-SN-TR Folha de dados(PDF) 9 Page - Microchip Technology |
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CAP1203-2-SN-TR Folha de dados(HTML) 9 Page - Microchip Technology |
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9 / 59 page  2013-2015 Microchip Technology Inc. DS00001572B-page 9 3.0 COMMUNICATIONS 3.1 Communications The CAP1203 communicates using the SMBus or I2C protocol. 3.2 System Management Bus The CAP1203 communicates with a host controller, such as an MCHP SIO, through the SMBus. The SMBus is a two- wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 3-1. Stretching of the SMCLK signal is supported; however, the CAP1203 will not stretch the clock sig- nal. 3.2.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 3.2.2 SMBUS ADDRESS AND RD / WR BIT The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the client device. 3.2.3 The CAP1203responds to SMBus address 0101_000(r/w). SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 3.2.4 SMBUS ACK AND NACK BITS The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto- cols. The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives except the last data byte. 3.2.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1203 detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. FIGURE 3-1: SMBUS TIMING DIAGRAM SM D A TA SM C LK T BU F P S S - Start C o ndition P - Stop C ondition P S T HIGH T LOW T HD :STA T SU :STO T HD :STA T HD :D AT T SU:D AT T SU :STA T FALL T RISE |
Nº de peça semelhante - CAP1203-2-SN-TR |
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Descrição semelhante - CAP1203-2-SN-TR |
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