WAKE

DONE

RSTn

DELAY/

M_RST

POR

RESISTANCE

READING

9

TPL5010

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SNAS651 – JANUARY 2015

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Feature Description (continued)

8.3.3 RSTn

To implement the reset interface between the TPL5010 and the uC a pull-up resistance is required. 100K

Ω is

recommended, to minimize current.

During the POR and the reading of the REXT the RSTn signal is LOW.

RSTn is asserted (LOW) for either one of the following conditions:

•

1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately

20ms).

•

2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising

edge (see Figure 8).

8.4 Device Functional Modes

8.4.1 Startup

During startup, after POR, the TPL5010 executes a one-time measurement of the resistance attached to the

DELAY/M_RST pin in order to determine the desired time interval for WAKE. This measurement interval is

Figure 9. Startup

8.4.2 Normal Operating Mode

During normal operating mode, the TPL5010 asserts periodic WAKE pulses in response to valid DONE pulses

from the uC. If either a manual reset is applied (logic HIGH on DELAY/M_RST pin) or the uC does not issue a

DONE pulse within the required time, the TPL5010 asserts the RSTn signal to the uC and restarts its internal

counters. See Figure 8 and Figure 10 .

8.5 Programming

8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin

The time interval between 2 adjacent WAKE pulses (rising edges) is selectable through an external resistance

The time between 2 adjacent RESET signals (falling edges) or between a RESET (falling edge) and a WAKE