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GS2961A Folha de dados(PDF) 10 Page - Semtech Corporation

Nome de Peças GS2961A
Descrição Electrónicos  HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
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Fabricante Electrônico  SEMTECH [Semtech Corporation]
Página de início  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

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GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
10 of 104
C7RESET_TRST
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
D4, E4, F4
PLL_GND
Input Power
GND pins for the Reclocker PLL. Connect to analog GND.
D5, E5, F5,
G4, G5, H3
CORE_GND
Input Power
GND connection for device core. Connect to digital GND.
D6, E6, F6,
G6
CORE_VDD
Input Power
POWER connection for device core. Connect to 1.2V DC digital.
D7
SW_EN
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.10.1.
D8
JTAG/HOST
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
E1
EQ_VDD
Input Power
POWER pin for SDI buffer. Connect to 3.3V DC analog.
E2
EQ_GND
Input Power
GND pin for SDI buffer. Connect to analog GND.
E7
SDOUT_TDO
Output
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
Note: GSPI is slightly different than the SPI. For more details on GSPI,
please refer to 4.19 GSPI - HOST Interface.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description


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