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ST16C2552 Folha de dados(PDF) 9 Page - Exar Corporation

Nome de Peças ST16C2552
Descrição Electrónicos  2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
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Fabricante Electrônico  EXAR [Exar Corporation]
Página de início  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C2552 Folha de dados(HTML) 9 Page - Exar Corporation

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ST16C2552
REV. 4.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
9
2.7
INTA and INTB Ouputs
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Tables 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 16
through 21.
2.8
Crystal Oscillator or Ext. Clock Input
The 2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. See “Programmable Baud Rate
Generator” on page 10.
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 2), with an external 500k
Ω to
1 M
Ω resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500 ΚΩ−1ΜΩ
XTAL1
XTAL2


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