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Si5348-D-EVB Folha de dados(PDF) 1 Page - Silicon Laboratories

Nome de Peças Si5348-D-EVB
Descrição Electrónicos  Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks
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Fabricante Electrônico  SILABS [Silicon Laboratories]
Página de início  http://www.silabs.com
Logo SILABS - Silicon Laboratories

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Si5348 Rev D Data Sheet
Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary
(T-BC) and Slave (T-SC) Clocks
The Si5348 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLsare individually configurable as a SyncE PLL, IEEE
1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digital-
ly controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588
(PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/
OCXO reference input to determine the device’s frequency accuracy and stability. The
Si5348 is programmable via a serial interface with in-circuit programmable non-volatile
memory so it always powers up into a known configuration. Programming the Si5348 is
easy with ClockBuilder Pro™ software. Factory pre-programmed devices are also availa-
ble.
Applications:
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization
KEY FEATURES
• Three independent DSPLLs in a single
monolithic IC supporting flexible SyncE/
IEEE 1588 and SETS architectures
• Ultra-low jitter of 100 fs
• Input frequency range:
• External crystal: 48 to 54 MHz
• REF clock: 5 to 250 MHz
• Diff clock: 8 kHz to 750 MHz
• LVCMOS clock: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 1 PPS to 712.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 &
2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253
(Stratum-3/3E)
DSPLL D
IN0
IN1
IN2
IN3
IN4
REF
TCXO/OCXO
REFb
OUT6
OUT5
OUT1
OUT4
OUT3
OUT2
OUT0
XB
XA
48-54 MHz XTAL
OSC
DSPLL C
DSPLL A
I2C / SPI
Control
NVM
Status Flags
Status Monitor
Si5348
÷FRAC
÷FRAC
÷FRAC
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0


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