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LM2742 Folha de dados(PDF) 9 Page - National Semiconductor (TI) |
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LM2742 Folha de dados(HTML) 9 Page - National Semiconductor (TI) |
9 / 22 page Block Diagram 20087501 Application Information THEORY OF OPERATION The LM2742 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck convert- ers. It has power good (PWRGD), and output shutdown (SD). Current limit is achieved by sensing the voltage V DS across the low side FET. During current limit the high side gate is turned off and the low side gate turned on. The soft start capacitor is discharged by a 95µA source (reducing the maximum duty cycle) until the current is under control. START UP When V CC exceeds 4.2V and the shutdown pin SD sees a logic high the soft start capacitor begins charging through an internal fixed 10µA source. During this time the output of the error amplifier is allowed to rise with the voltage of the soft start capacitor. This capacitor, C SS, determines soft start time, and can be determined approximately by: An application for a microprocessor might need a delay of 3ms, in which case C SS would be 12nF. For a different device, a 100ms delay might be more appropriate, in which case C SS would be 400nF. (390 10%) During soft start the PWRGD flag is forced low and is released when the voltage reaches a set value. At this point this chip enters normal operation mode and the Power Good flag is released. Since the output is floating when the LM2742 is turned off, it is possible that the output capacitor may be precharged to some positive value. During start-up, the LM2742 operates fully synchronous and will discharge the output capacitor to some extent depending on the output voltage, soft start capacitance, and the size of the output capacitor. NORMAL OPERATION While in normal operation mode, the LM2742 regulates the output voltage by controlling the duty cycle of the high side and low side FETs. The equation governing output voltage is: V O =0.6x(RFB1 +RFB2)/RFB1 The PWM frequency is adjustable between 50kHz and 2MHz and is set by an external resistor, R FADJ, between the FREQ pin and ground. The resistance needed for a desired frequency is approximately: www.national.com 9 |
Nº de peça semelhante - LM2742 |
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Descrição semelhante - LM2742 |
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