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SLB9665XQ2.0 Folha de dados(PDF) 7 Page - Infineon Technologies AG |
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SLB9665XQ2.0 Folha de dados(HTML) 7 Page - Infineon Technologies AG |
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7 / 24 page  Data Sheet 7 Revision 1.0 2015-10-27 SLB 9665 TPM2.0 Trusted Platform Module LPC Interface 2.2 Localities The interface explicitly does not support standard IO cycles (read and write). This implies that IO-mapped addressing of the device is not possible; only accesses via the locality-based TPM-type cycles are possible which also means that “locality none” as defined in [4] is not supported as well. For a detailed description of the locality addressing scheme and the registers located in each locality, please refer to [4] as well. 2.3 Power Management The SLB 9665 does not support the LPC power down signal (signal LPCPD) or the clock run protocol (signal CLKRUN). Power management is handled internally; no explicit power-down or standby mode is available. The device automatically enters a low-power state after each successful command/response transaction. If a transaction is started on the LPC bus from the host platform, the device will wake immediately and will return to the low-power mode after 30 seconds of inactivity after the last TPM command has been executed. 2.4 LPC Access Rights The registers located in the address space of the SLB 9665 are described in the respective TCG document (please refer to [4]). The registers READFIFO and WRITEFIFO mentioned in Table 2-1 below refer to the DATAFIFO register, the names are used to state whether this register is read or written. Each register has its own access rights which describe if the register is updated on a write or can be read if the associated ACTIVE.LOCALITY is set respectively not set. If the access cycle is not accepted by the TPM, it will be master aborted (no LPC SYNC cycle will be generated and no action is done on the internal registers). Table 2-1 shows which operation is done by the TPM on each register depending on the ACTIVE.LOCALITY bit. Note: In Table 2-1, “abort” means that no valid SYNC is generated when a cycle is seen by the interface which shall be aborted. The data present in an aborted write access cycle does not change the addressed register. Table 2-1 LT Register Access Matrix ACTIVE.LOCALITY set for this locality ACTIVE.LOCALITY set for different LOCALITY ACTIVE.LOCALITY not set READ WRITE READ WRITE READ WRITE STS read write abort abort abort abort INT.ENABLE read write read abort read abort INT.VECTOR read write read abort read abort INT.STATUS read reset interrupt read abort read abort INT.CAPABILITY read - (abort) read - (abort) read - (abort) ACCESS read write read write read write READFIFO read1) abort abort abort abort abort WRITEFIFO abort write abort abort abort abort Configuration Registers read write read abort read abort HASH.START abort write abort abort abort write2) |
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